Verilog Bitfield

Bitfield renders hardware bitfield definitions as interactive SVG diagrams and tables. Write name width description in a code block, indent sub-fields, and the plugin handles the rest — bit-range calculation, reserved padding, overflow detection, color assignment. Works for register maps, interface protocols, packet headers, and any fixed-width bit layout. One code block can define multiple blocks. Use @references to compose complex definitions from modular pieces without duplication. Click a reference to jump to its definition, hover for instant preview. Toggle between diagram and table per block. Diagrams auto-select horizontal or vertical layout based on width. Tables show field name, bit range, and description with nested indentation. Your bitfield spec lives in your notes, rendered live, always in sync with your design.